Sputter-etch tool and liners

ABSTRACT

This disclosure provides systems, methods and apparatus for fabricating electromechanical system devices within a plasma-etch reaction chamber. In one aspect, a plasma-etch system includes a plasma-etch reaction chamber, an inlet in fluid communication with the reaction chamber, a cathode positioned within the reaction chamber and a non-hollow anode positioned within the reaction chamber between the inlet and the cathode. The inlet is configured to introduce a process gas into the reaction chamber such that at least a portion of the process gas strikes an upper surface of the anode and is allowed to flow across the upper surface and around the edges of the anode. The anode can be a liner plate in place of a showerhead.

TECHNICAL FIELD

This disclosure relates to an apparatus for etching, and more particularly, to a plasma-etch reaction chamber.

DESCRIPTION OF THE RELATED TECHNOLOGY

Electromechanical systems include devices having electrical and mechanical elements, actuators, transducers, sensors, optical components (e.g., mirrors) and electronics. Electromechanical systems can be manufactured at a variety of scales including, but not limited to, microscales and nanoscales. For example, microelectromechanical systems (MEMS) devices can include structures having sizes ranging from about a micron to hundreds of microns or more. Nanoelectromechanical systems (NEMS) devices can include structures having sizes smaller than a micron including, for example, sizes smaller than several hundred nanometers. Electromechanical elements may be created using deposition, etching, lithography, and/or other micromachining processes that etch away parts of substrates and/or deposited material layers, or that add layers to form electrical and electromechanical devices.

One type of electromechanical systems device is called an interferometric modulator (IMOD). As used herein, the term interferometric modulator or interferometric light modulator refers to a device that selectively absorbs and/or reflects light using the principles of optical interference. In some implementations, an interferometric modulator may include a pair of conductive plates, one or both of which may be transparent and/or reflective, wholly or in part, and capable of relative motion upon application of an appropriate electrical signal. In an implementation, one plate may include a stationary layer deposited on a substrate and the other plate may include a metallic membrane separated from the stationary layer by an air gap. The position of one plate in relation to another can change the optical interference of light incident on the interferometric modulator. Interferometric modulator devices have a wide range of applications, and are anticipated to be used in improving existing products and creating new products, especially those with display capabilities.

The aforementioned electromechanical systems devices can be fabricated using various processing tools, such as the deposition and etch (e.g., plasma-etch) tools of a type that can also be employed to fabricate integrated circuits (ICs).

SUMMARY

The systems, methods and devices of the disclosure each have several innovative aspects, no single one of which is solely responsible for the desirable attributes disclosed herein.

One innovative aspect of the subject matter described in this disclosure can be implemented in a plasma-etch system. The plasma-etch system includes a plasma-etch reaction chamber, an inlet, a cathode and a non-hollow anode. The inlet can be configured to be in fluid communication with the reaction chamber. The cathode can include a substrate support positioned within the reaction chamber. The non-hollow anode can be positioned within the reaction chamber between the inlet and the cathode. The inlet can be configured to introduce a process gas into the reaction chamber such that at least a portion of the process gas is allowed to flow across an upper surface of the anode and around edges of the anode.

In some implementations, the plasma-etch reaction chamber can include a sputter-etch reaction chamber. In some implementations, the anode can be substantially unperforated through its thickness.

Another innovative aspect of the subject matter described in this disclosure can be implemented in a plasma-etch system. The plasma-etch system includes a chamber for a plasma-etch reaction, cathode means for conducting electric charges, anode means for conducting electric charges, and fluid communication means. The fluid communication means can be for providing fluid into the chamber and guiding at least some of the fluid across an upper surface of the anode means, around outer edges of the anode means and into a plasma reaction zone between the anode means and the cathode means.

In some implementations, the chamber can include a sputter-etch reaction chamber. In some implementations, the fluid communication means can includes a gas inlet and the anode means includes a non-hollow plate positioned between the gas inlet and the cathode means.

Another innovative aspect of the subject matter described in this disclosure can be implemented in a method of plasma-etching a substrate. The method of plasma-etching a substrate can include providing a plasma-etch reaction chamber, an inlet configured to be in fluid communication with the reaction chamber, a cathode configured to support a substrate, and an anode within the reaction chamber between the inlet and the cathode. The cathode can be configured to be negatively biased with respect to the anode. The method can include introducing a process gas into the reaction chamber such that at least a portion of the process gas strikes an upper surface of the anode and flows across the upper surface and around the edges of the anode. The method can include igniting a plasma between the anode and the cathode.

In some implementations, the method of plasma-etching a substrate can also include etching material from at least a portion of a substrate supported by the cathode. In some implementations, etching can include sputter-etching.

Details of one or more implementations of the subject matter described in this specification are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages will become apparent from the description, the drawings, and the claims. Note that the relative dimensions of the following figures may not be drawn to scale.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows an example of an isometric view depicting two adjacent pixels in a series of pixels of an interferometric modulator (IMOD) display device.

FIG. 2 shows an example of a system block diagram illustrating an electronic device incorporating a 3×3 interferometric modulator display.

FIG. 3 shows an example of a diagram illustrating movable reflective layer position versus applied voltage for the interferometric modulator of FIG. 1.

FIG. 4 shows an example of a table illustrating various states of an interferometric modulator when various common and segment voltages are applied.

FIG. 5A shows an example of a diagram illustrating a frame of display data in the 3×3 interferometric modulator display of FIG. 2.

FIG. 5B shows an example of a timing diagram for common and segment signals that may be used to write the frame of display data illustrated in FIG. 5A.

FIG. 6A shows an example of a partial cross-section of the interferometric modulator display of FIG. 1.

FIGS. 6B-6E show examples of cross-sections of varying implementations of interferometric modulators.

FIG. 7 shows a flow diagram illustrating an example of a manufacturing process for an interferometric modulator.

FIGS. 8A-8E show examples of cross-sectional schematic illustrations of various stages in a method of making an interferometric modulator.

FIG. 9 shows an example of a cross-sectional schematic illustration of a stage in fabricating an interferometric modulator device.

FIG. 10A shows an example of a cross-sectional side view of a plasma-etch system.

FIG. 10B shows an example of a cross-sectional top view of a plasma-etch system taken along lines 10B-10B of FIG. 10A.

FIG. 10C shows an example of a cross-sectional side view of a plasma-etch system.

FIG. 10D shows an example of a cross-sectional top view of a plasma-etch system taken along lines 10D-10D of FIG. 10C.

FIG. 10E shows an example of a system block diagram illustrating a plasma-etch system including a plasma-etch reactor and a control system.

FIG. 10F shows an example of a flow diagram illustrating a method of plasma-etching a substrate.

FIGS. 11A and 11B show examples of system block diagrams illustrating a display device that includes a plurality of interferometric modulators.

Like reference numbers and designations in the various drawings indicate like elements.

DETAILED DESCRIPTION

The following detailed description is directed to certain implementations for the purposes of describing the innovative aspects. However, the teachings herein can be applied in a multitude of different ways. The described implementations may be implemented in any device that is configured to display an image, whether in motion (e.g., video) or stationary (e.g., still image), and whether textual, graphical or pictorial. More particularly, it is contemplated that the implementations may be implemented in or associated with a variety of electronic devices such as, but not limited to, mobile telephones, multimedia Internet enabled cellular telephones, mobile television receivers, wireless devices, smartphones, bluetooth devices, personal data assistants (PDAs), wireless electronic mail receivers, hand-held or portable computers, netbooks, notebooks, smartbooks, printers, copiers, scanners, facsimile devices, GPS receivers/navigators, cameras, MP3 players, camcorders, game consoles, wrist watches, clocks, calculators, television monitors, flat panel displays, electronic reading devices (e.g., e-readers), computer monitors, auto displays (e.g., odometer display, etc.), cockpit controls and/or displays, camera view displays (e.g., display of a rear view camera in a vehicle), electronic photographs, electronic billboards or signs, projectors, architectural structures, microwaves, refrigerators, stereo systems, cassette recorders or players, DVD players, CD players, VCRs, radios, portable memory chips, washers, dryers, washer/dryers, packaging (e.g., electromechanical systems (EMS), MEMS and non-MEMS), aesthetic structures (e.g., display of images on a piece of jewelry) and a variety of electromechanical systems devices. The teachings herein also can be used in non-display applications such as, but not limited to, electronic switching devices, radio frequency filters, sensors, accelerometers, gyroscopes, motion-sensing devices, magnetometers, inertial components for consumer electronics, parts of consumer electronics products, varactors, liquid crystal devices, electrophoretic devices, drive schemes, manufacturing processes, electronic test equipment. Thus, the teachings are not intended to be limited to the implementations depicted solely in the Figures, but instead have wide applicability as will be readily apparent to one having ordinary skill in the art.

A plasma-etch system is disclosed that can be used to fabricate a device (e.g., a MEMS device). The plasma-etch system can include a reaction chamber, an inlet configured to introduce a process gas (e.g., argon) into the reaction chamber, an anode, and a cathode. The system can be configured to perform a plasma-etch process, and particularly a sputter-etch process, on a substrate supported by the cathode within the reaction chamber. In place of a showerhead plenum, the plasma-etch system can include a non-hollow anode. The anode can include a liner plate positioned between the inlet and the cathode configured such that at least a portion of the process gas can strike an upper surface of the liner plate and flow across the upper surface and around the edges of the plate. In some implementations, at least a portion of the process gas can flow through the liner plate. In some implementations, the liner plate can include an un-anodized material.

Particular implementations of the subject matter described in this disclosure can be implemented to realize one or more of the following potential advantages. A substantially solid or non-hollow anode under the inlet can aid in distributing gases for the plasma etch without the higher surface area, plenums, and holes of a showerhead. Showerhead plenums create trapped spaces and high surface areas that retain moisture and contaminants, entailing very long pump-down cycle times to reach desired moisture and/or contaminant levels within the reaction chamber of some conventional tools. In contrast, the non-hollow anode in some implementations disclosed herein can reduce pump-down times, relative to a showerhead for the same moisture/contaminant levels, thus increasing tool throughput. In some implementations, the anode can include a bare metal, such as molybdenum, stainless steel, and/or aluminum, without anodization, which can further reduce moisture absorption and pump-down time. The material selected for the non-hollow anode can be beadblasted or sandblasted to provide surface roughness, as described further herein. The non-hollow anode can include a liner plate as described further herein.

One example of a suitable MEMS device, to which the described implementations may apply, is a reflective display device. Reflective display devices can incorporate interferometric modulators (IMODs) to selectively absorb and/or reflect light incident thereon using principles of optical interference. IMODs can include an absorber, a reflector that is movable with respect to the absorber, and an optical resonant cavity defined between the absorber and the reflector. The reflector can be moved to two or more different positions, which can change the size of the optical resonant cavity and thereby affect the reflectance of the interferometric modulator. The reflectance spectrums of IMODs can create fairly broad spectral bands which can be shifted across the visible wavelengths to generate different colors. The position of the spectral band can be adjusted by changing the thickness of the optical resonant cavity, i.e., by changing the position of the reflector.

FIG. 1 shows an example of an isometric view depicting two adjacent pixels in a series of pixels of an interferometric modulator (IMOD) display device. The IMOD display device includes one or more interferometric MEMS display elements. In these devices, the pixels of the MEMS display elements can be in either a bright or dark state. In the bright (“relaxed,” “open” or “on”) state, the display element reflects a large portion of incident visible light, e.g., to a user. Conversely, in the dark (“actuated,” “closed” or “off”) state, the display element reflects little incident visible light. In some implementations, the light reflectance properties of the on and off states may be reversed. MEMS pixels can be configured to reflect predominantly at particular wavelengths allowing for a color display in addition to black and white.

The IMOD display device can include a row/column array of IMODs. Each IMOD can include a pair of reflective layers, i.e., a movable reflective layer and a fixed partially reflective layer, positioned at a variable and controllable distance from each other to form an air gap (also referred to as an optical gap or cavity). The movable reflective layer may be moved between at least two positions. In a first position, i.e., a relaxed position, the movable reflective layer can be positioned at a relatively large distance from the fixed partially reflective layer. In a second position, i.e., an actuated position, the movable reflective layer can be positioned more closely to the partially reflective layer. Incident light that reflects from the two layers can interfere constructively or destructively depending on the position of the movable reflective layer, producing either an overall reflective or non-reflective state for each pixel. In some implementations, the IMOD may be in a reflective state when unactuated, reflecting light within the visible spectrum, and may be in a dark state when unactuated, reflecting light outside of the visible range (e.g., infrared light). In some other implementations, however, an IMOD may be in a dark state when unactuated, and in a reflective state when actuated. In some implementations, the introduction of an applied voltage can drive the pixels to change states. In some other implementations, an applied charge can drive the pixels to change states.

The depicted portion of the pixel array in FIG. 1 includes two adjacent the interferometric modulators 12. In the IMOD 12 on the left (as illustrated), a movable reflective layer 14 is illustrated in a relaxed position at a predetermined distance from an optical stack 16, which includes a partially reflective layer. The voltage V₀ applied across the IMOD 12 on the left is insufficient to cause actuation of the movable reflective layer 14. In the IMOD 12 on the right, the movable reflective layer 14 is illustrated in an actuated position near or adjacent the optical stack 16. The voltage V_(bias) applied across the IMOD 12 on the right is sufficient to maintain the movable reflective layer 14 in the actuated position.

In FIG. 1, the reflective properties of the pixels 12 are generally illustrated with arrows 13 indicating light incident upon the pixels 12, and light 15 reflecting from the pixel 12 on the left. Although not illustrated in detail, it will be understood by one having ordinary skill in the art that most of the light 13 incident upon the pixels 12 will be transmitted through the transparent substrate 20, toward the optical stack 16. A portion of the light incident upon the optical stack 16 will be transmitted through the partially reflective layer of the optical stack 16, and a portion will be reflected back through the transparent substrate 20. The portion of the light 13 that is transmitted through the optical stack 16 will be reflected at the movable reflective layer 14, back toward (and through) the transparent substrate 20. Interference (constructive or destructive) between the light reflected from the partially reflective layer of the optical stack 16 and the light reflected from the movable reflective layer 14 will determine the wavelength(s) of the light 15 reflected from the pixel 12.

The optical stack 16 can include a single layer or several layers. The layer(s) can include one or more of an electrode layer, a partially reflective and partially transmissive layer and a transparent dielectric layer. In some implementations, the optical stack 16 is electrically conductive, partially transparent and partially reflective, and may be fabricated, for example, by depositing one or more of the above layers onto a transparent substrate 20. The electrode layer can be formed from a variety of materials, such as various metals, for example indium tin oxide (ITO). The partially reflective layer can be formed from a variety of materials that are partially reflective, such as various metals, e.g., chromium (Cr), semiconductors, and dielectrics. The partially reflective layer can be formed of one or more layers of materials, and each of the layers can be formed of a single material or a combination of materials. In some implementations, the optical stack 16 can include a single semi-transparent thickness of metal or semiconductor which serves as both an optical absorber and conductor, while different, more conductive layers or portions (e.g., of the optical stack 16 or of other structures of the IMOD) can serve to bus signals between IMOD pixels. The optical stack 16 also can include one or more insulating or dielectric layers covering one or more conductive layers or a conductive/absorptive layer.

In some implementations, the layer(s) of the optical stack 16 can be patterned into parallel strips, and may form row electrodes in a display device as described further below. As will be understood by one having skill in the art, the term “patterned” is used herein to refer to masking as well as etching processes. In some implementations, a highly conductive and reflective material, such as aluminum (Al), may be used for the movable reflective layer 14, and these strips may form column electrodes in a display device. The movable reflective layer 14 may be formed as a series of parallel strips of a deposited metal layer or layers (orthogonal to the row electrodes of the optical stack 16) to form columns deposited on top of posts 18 and an intervening sacrificial material deposited between the posts 18. When the sacrificial material is etched away, a defined gap 19, or optical cavity, can be formed between the movable reflective layer 14 and the optical stack 16. In some implementations, the spacing between the posts 18 may be approximately 1-1000 um, while the gap 19 may be less than 10,000 Angstroms (Å).

In some implementations, each pixel of the IMOD, whether in the actuated or relaxed state, is essentially a capacitor formed by the fixed and moving reflective layers. When no voltage is applied, the movable reflective layer 14 a remains in a mechanically relaxed state, as illustrated by the pixel 12 on the left in FIG. 1, with the gap 19 between the movable reflective layer 14 and the optical stack 16. However, when a potential difference, e.g., voltage, is applied to at least one of a selected row and column, the capacitor formed at the intersection of the row and column electrodes at the corresponding pixel becomes charged, and electrostatic forces pull the electrodes together. If the applied voltage exceeds a threshold, the movable reflective layer 14 can deform and move near or against the optical stack 16. A dielectric layer (not shown) within the optical stack 16 may prevent shorting and control the separation distance between the layers 14 and 16, as illustrated by the actuated pixel 12 on the right in FIG. 1. The behavior is the same regardless of the polarity of the applied potential difference. Though a series of pixels in an array may be referred to in some instances as “rows” or “columns,” a person having ordinary skill in the art will readily understand that referring to one direction as a “row” and another as a “column” is arbitrary. Restated, in some orientations, the rows can be considered columns, and the columns considered to be rows. Furthermore, the display elements may be evenly arranged in orthogonal rows and columns (an “array”), or arranged in non-linear configurations, for example, having certain positional offsets with respect to one another (a “mosaic”). The terms “array” and “mosaic” may refer to either configuration. Thus, although the display is referred to as including an “array” or “mosaic,” the elements themselves need not be arranged orthogonally to one another, or disposed in an even distribution, in any instance, but may include arrangements having asymmetric shapes and unevenly distributed elements.

FIGS. 2 through 5B illustrate one example of a process and one example of a system for using an array of interferometric modulators in a display application.

FIG. 2 shows an example of a system block diagram illustrating an electronic device incorporating a 3×3 interferometric modulator display. The electronic device includes a processor 21 that may be configured to execute one or more software modules. In addition to executing an operating system, the processor 21 may be configured to execute one or more software applications, including a web browser, a telephone application, an email program, or any other software application.

The processor 21 can be configured to communicate with an array driver 22. The array driver 22 can include a row driver circuit 24 and a column driver circuit 26 that provide signals to, e.g., a display array or panel 30. The cross section of the IMOD display device illustrated in FIG. 1 is shown by the lines 1-1 in FIG. 2. Although FIG. 2 illustrates a 3×3 array of IMODs for the sake of clarity, the display array 30 may contain a very large number of IMODs, and may have a different number of IMODs in rows than in columns, and vice versa.

FIG. 3 shows an example of a diagram illustrating movable reflective layer position versus applied voltage for the interferometric modulator of FIG. 1. For MEMS interferometric modulators, the row/column (i.e., common/segment) write procedure may take advantage of a hysteresis property of these devices as illustrated in FIG. 3. An interferometric modulator may require, for example, about a 10-volt potential difference to cause the movable reflective layer, or mirror, to change from the relaxed state to the actuated state. When the voltage is reduced from that value, the movable reflective layer maintains its state as the voltage drops back below, e.g., 10-volts, however, the movable reflective layer does not relax completely until the voltage drops below 2-volts. Thus, a range of voltage, approximately 3 to 7-volts, as shown in FIG. 3, exists where there is a window of applied voltage within which the device is stable in either the relaxed or actuated state. This is referred to herein as the “hysteresis window” or “stability window.” For a display array 30 having the hysteresis characteristics of FIG. 3, the row/column write procedure can be designed to address one or more rows at a time, such that during the addressing of a given row, pixels in the addressed row that are to be actuated are exposed to a voltage difference of about 10-volts, and pixels that are to be relaxed are exposed to a voltage difference of near zero volts. After addressing, the pixels are exposed to a steady state or bias voltage difference of approximately 5-volts such that they remain in the previous strobing state. In this example, after being addressed, each pixel sees a potential difference within the “stability window” of about 3-7-volts. This hysteresis property feature enables the pixel design, e.g., illustrated in FIG. 1, to remain stable in either an actuated or relaxed pre-existing state under the same applied voltage conditions. Since each IMOD pixel, whether in the actuated or relaxed state, is essentially a capacitor formed by the fixed and moving reflective layers, this stable state can be held at a steady voltage within the hysteresis window without substantially consuming or losing power. Moreover, essentially little or no current flows into the IMOD pixel if the applied voltage potential remains substantially fixed.

In some implementations, a frame of an image may be created by applying data signals in the form of “segment” voltages along the set of column electrodes, in accordance with the desired change (if any) to the state of the pixels in a given row. Each row of the array can be addressed in turn, such that the frame is written one row at a time. To write the desired data to the pixels in a first row, segment voltages corresponding to the desired state of the pixels in the first row can be applied on the column electrodes, and a first row pulse in the form of a specific “common” voltage or signal can be applied to the first row electrode. The set of segment voltages can then be changed to correspond to the desired change (if any) to the state of the pixels in the second row, and a second common voltage can be applied to the second row electrode. In some implementations, the pixels in the first row are unaffected by the change in the segment voltages applied along the column electrodes, and remain in the state they were set to during the first common voltage row pulse. This process may be repeated for the entire series of rows, or alternatively, columns, in a sequential fashion to produce the image frame. The frames can be refreshed and/or updated with new image data by continually repeating this process at some desired number of frames per second.

The combination of segment and common signals applied across each pixel (that is, the potential difference across each pixel) determines the resulting state of each pixel. FIG. 4 shows an example of a table illustrating various states of an interferometric modulator when various common and segment voltages are applied. As will be readily understood by one having ordinary skill in the art, the “segment” voltages can be applied to either the column electrodes or the row electrodes, and the “common” voltages can be applied to the other of the column electrodes or the row electrodes.

As illustrated in FIG. 4 (as well as in the timing diagram shown in FIG. 5B), when a release voltage VC_(REL) is applied along a common line, all interferometric modulator elements along the common line will be placed in a relaxed state, alternatively referred to as a released or unactuated state, regardless of the voltage applied along the segment lines, i.e., high segment voltage VS_(H) and low segment voltage VS_(L). In particular, when the release voltage VC_(REL) is applied along a common line, the potential voltage across the modulator (alternatively referred to as a pixel voltage) is within the relaxation window (see FIG. 3, also referred to as a release window) both when the high segment voltage VS_(H) and the low segment voltage VS_(L) are applied along the corresponding segment line for that pixel.

When a hold voltage is applied on a common line, such as a high hold voltage VC_(HOLD) _(—) _(H) or a low hold voltage VC_(HOLD) _(—) _(L), the state of the interferometric modulator will remain constant. For example, a relaxed IMOD will remain in a relaxed position, and an actuated IMOD will remain in an actuated position. The hold voltages can be selected such that the pixel voltage will remain within a stability window both when the high segment voltage VS_(H) and the low segment voltage VS_(L) are applied along the corresponding segment line. Thus, the segment voltage swing, i.e., the difference between the high VS_(H) and low segment voltage VS_(L), is less than the width of either the positive or the negative stability window.

When an addressing, or actuation, voltage is applied on a common line, such as a high addressing voltage VC_(ADD) _(—) _(H) or a low addressing voltage VC_(ADD) _(—) _(L), data can be selectively written to the modulators along that line by application of segment voltages along the respective segment lines. The segment voltages may be selected such that actuation is dependent upon the segment voltage applied. When an addressing voltage is applied along a common line, application of one segment voltage will result in a pixel voltage within a stability window, causing the pixel to remain unactuated. In contrast, application of the other segment voltage will result in a pixel voltage beyond the stability window, resulting in actuation of the pixel. The particular segment voltage which causes actuation can vary depending upon which addressing voltage is used. In some implementations, when the high addressing voltage VC_(ADD) _(—) _(H) is applied along the common line, application of the high segment voltage VS_(H) can cause a modulator to remain in its current position, while application of the low segment voltage VS_(L) can cause actuation of the modulator. As a corollary, the effect of the segment voltages can be the opposite when a low addressing voltage VC_(ADD) _(—) _(L) is applied, with high segment voltage VS_(H) causing actuation of the modulator, and low segment voltage VS_(L) having no effect (i.e., remaining stable) on the state of the modulator.

In some implementations, hold voltages, address voltages, and segment voltages may be used which produce the same polarity potential difference across the modulators. In some other implementations, signals can be used which alternate the polarity of the potential difference of the modulators. Alternation of the polarity across the modulators (that is, alternation of the polarity of write procedures) may reduce or inhibit charge accumulation which could occur after repeated write operations of a single polarity.

FIG. 5A shows an example of a diagram illustrating a frame of display data in the 3×3 interferometric modulator display of FIG. 2. FIG. 5B illustrates an example of a timing diagram for common and segment signals that may be used to write the frame of display data illustrated in FIG. 5A. The signals can be applied to the, e.g., 3×3 array of FIG. 2, which will ultimately result in the line time 60 e display arrangement illustrated in FIG. 5A. The actuated modulators in FIG. 5A are in a dark-state, i.e., where a substantial portion of the reflected light is outside of the visible spectrum so as to result in a dark appearance to, e.g., a viewer. Prior to writing the frame illustrated in FIG. 5A, the pixels can be in any state, but the write procedure illustrated in the timing diagram of FIG. 5B presumes that each modulator has been released and resides in an unactuated state before the first line time 60 a.

During the first line time 60 a: a release voltage 70 is applied on common line 1; the voltage applied on common line 2 begins at a high hold voltage 72 and moves to a release voltage 70; and a low hold voltage 76 is applied along common line 3. Thus, the modulators (common 1, segment 1), (1,2) and (1,3) along common line 1 remain in a relaxed, or unactuated, state for the duration of the first line time 60 a, the modulators (2,1), (2,2) and (2,3) along common line 2 will move to a relaxed state, and the modulators (3,1), (3,2) and (3,3) along common line 3 will remain in their previous state. With reference to FIG. 4, the segment voltages applied along segment lines 1, 2 and 3 will have no effect on the state of the interferometric modulators, as none of common lines 1, 2 or 3 are being exposed to voltage levels causing actuation during line time 60 a (i.e., VC_(REL)—relax and VC_(HOLD) _(—) _(L)—stable).

During the second line time 60 b, the voltage on common line 1 moves to a high hold voltage 72, and all modulators along common line 1 remain in a relaxed state regardless of the segment voltage applied because no addressing, or actuation, voltage was applied on the common line 1. The modulators along common line 2 remain in a relaxed state due to the application of the release voltage 70, and the modulators (3,1), (3,2) and (3,3) along common line 3 will relax when the voltage along the common line 3 moves to a release voltage 70.

During the third line time 60 c, common line 1 is addressed by applying a high address voltage 74 on common line 1. Because a low segment voltage 64 is applied along segment lines 1 and 2 during the application of this address voltage, the pixel voltage across modulators (1,1) and (1,2) is greater than the high end of the positive stability window (i.e., the voltage differential exceeded a predefined threshold) of the modulators, and the modulators (1,1) and (1,2) are actuated. Conversely, because a high segment voltage 62 is applied along segment line 3, the pixel voltage across modulator (1,3) is less than that of modulators (1,1) and (1,2), and remains within the positive stability window of the modulator; modulator (1,3) thus remains relaxed. Also during line time 60 c, the voltage along common line 2 decreases to a low hold voltage 76, and the voltage along common line 3 remains at a release voltage 70, leaving the modulators along common lines 2 and 3 in a relaxed position.

During the fourth line time 60 d, the voltage on common line 1 returns to a high hold voltage 72, leaving the modulators along common line 1 in their respective addressed states. The voltage on the common line 2 is decreased to a low address voltage 78. Because a high segment voltage 62 is applied along segment line 2, the pixel voltage across modulator (2,2) is below the lower end of the negative stability window of the modulator, causing the modulator (2,2) to actuate. Conversely, because a low segment voltage 64 is applied along segment lines 1 and 3, modulators (2,1) and (2,3) remain in a relaxed position. The voltage on common line 3 increases to a high hold voltage 72, leaving the modulators along common line 3 in a relaxed state.

Finally, during the fifth line time 60 e, the voltage on common line 1 remains at high hold voltage 72, and the voltage on common line 2 remains at a low hold voltage 76, leaving the modulators along common lines 1 and 2 in their respective addressed states. The voltage on common line 3 increases to a high address voltage 74 to address the modulators along common line 3. As a low segment voltage 64 is applied on segment lines 2 and 3, modulators (3,2) and (3,3) actuate, while the high segment voltage 62 applied along segment line 1 causes modulator (3,1) to remain in a relaxed position. Thus, at the end of the fifth line time 60 e, the 3×3 pixel array is in the state shown in FIG. 5A, and will remain in that state as long as the hold voltages are applied along the common lines, regardless of variations in the segment voltage which may occur when modulators along other common lines (not shown) are being addressed.

In the timing diagram of FIG. 5B, a given write procedure (i.e., line times 60 a-60 e) can include the use of either high hold and address voltages, or low hold and address voltages. Once the write procedure has been completed for a given common line (and the common voltage is set to the hold voltage having the same polarity as the actuation voltage), the pixel voltage remains within a given stability window, and does not pass through the relaxation window until a release voltage is applied on that common line. Furthermore, as each modulator is released as part of the write procedure prior to addressing the modulator, the actuation time of a modulator, rather than the release time, may determine the line time. Specifically, in implementations in which the release time of a modulator is greater than the actuation time, the release voltage may be applied for longer than a single line time, as depicted in FIG. 5B. In some other implementations, voltages applied along common lines or segment lines may vary to account for variations in the actuation and release voltages of different modulators, such as modulators of different colors.

The details of the structure of interferometric modulators that operate in accordance with the principles set forth above may vary widely. For example, FIGS. 6A-6E show examples of varying implementations of interferometric modulators, including the movable reflective layer 14 and its supporting structures. FIG. 6A shows an example of a partial cross-section of the interferometric modulator display of FIG. 1, where a strip of metal material, i.e., the movable reflective layer 14 is deposited on the supports 18 extending orthogonally from the substrate 20. In FIG. 6B, the movable reflective layer 14 of each IMOD is generally square or rectangular in shape and attached to supports at or near the corners, on the tethers 32. In FIG. 6C, the movable reflective layer 14 is generally square or rectangular in shape and suspended from a deformable layer 34, which may include a flexible metal. The deformable layer 34 can connect, directly or indirectly, to the substrate 20 around the perimeter of the movable reflective layer 14. These connections are herein referred to as support posts. The implementation shown in FIG. 6C has additional benefits deriving from the decoupling of the optical functions of the movable reflective layer 14 from its mechanical functions, which are carried out by the deformable layer 34. This decoupling allows the structural design and materials used for the reflective layer 14 and those used for the deformable layer 34 to be optimized independently of one another.

FIG. 6D shows another example of an IMOD, where the movable reflective layer 14 includes a reflective sub-layer 14 a. The movable reflective layer 14 rests on a support structure, such as the support posts 18. The support posts 18 provide separation of the movable reflective layer 14 from the lower stationary electrode (i.e., part of the optical stack 16 in the illustrated IMOD) so that a gap 19 is formed between the movable reflective layer 14 and the optical stack 16, for example when the movable reflective layer 14 is in a relaxed position. The movable reflective layer 14 also can include a conductive layer 14 c, which may be configured to serve as an electrode, and a support layer 14 b. In this example, the conductive layer 14 c is disposed on one side of the support layer 14 b, distal from the substrate 20, and the reflective sub-layer 14 a is disposed on the other side of the support layer 14 b, proximal to the substrate 20. In some implementations, the reflective sub-layer 14 a can be conductive and can be disposed between the support layer 14 b and the optical stack 16. The support layer 14 b can include one or more layers of a dielectric material, for example, silicon oxynitride (SiON) or silicon dioxide (SiO₂). In some implementations, the support layer 14 b can be a stack of layers, such as, for example, a SiO₂/SiON/SiO₂ tri-layer stack. Either or both of the reflective sub-layer 14 a and the conductive layer 14 c can include, e.g., an Al alloy with about 0.5% Cu, or another reflective metallic material. Employing the conductive layers 14 a, 14 c above and below the dielectric support layer 14 b can balance stresses and provide enhanced conduction. In some implementations, the reflective sub-layer 14 a and the conductive layer 14 c can be formed of different materials for a variety of design purposes, such as achieving specific stress profiles within the movable reflective layer 14.

As illustrated in FIG. 6D, some implementations also can include a black mask structure 23. The black mask structure 23 can be formed in optically inactive regions (e.g., between pixels or under the posts 18) to absorb ambient or stray light. The black mask structure 23 also can improve the optical properties of a display device by inhibiting light from being reflected from or transmitted through inactive portions of the display, thereby increasing the contrast ratio. Additionally, the black mask structure 23 can be conductive and be configured to function as an electrical bussing layer. In some implementations, the row electrodes can be connected to the black mask structure 23 to reduce the resistance of the connected row electrode. The black mask structure 23 can be formed using a variety of methods, including deposition and patterning techniques. The black mask structure 23 can include one or more layers. For example, in some implementations, the black mask structure 23 includes a molybdenum-chromium (MoCr) layer that serves as an optical absorber, a SiO₂ layer, and an aluminum alloy that serves as a reflector and a bussing layer, with a thickness in the range of about 30-80 Å, 500-1000 Å, and 500-6000 Å, respectively. The one or more layers can be patterned using a variety of techniques, including photolithography and dry etching, including, for example, tetrafluoromethane (CF₄) and/or oxygen (O₂) for the MoCr and SiO₂ layers and chlorine (Cl₂) and/or boron trichloride (BCl₃) for the aluminum alloy layer. In some implementations, the black mask 23 can be an etalon or interferometric stack structure. In such interferometric stack black mask structures 23, the conductive absorbers can be used to transmit or bus signals between lower, stationary electrodes in the optical stack 16 of each row or column. In some implementations, a spacer layer 35 can serve to generally electrically isolate the absorber layer 16 a from the conductive layers in the black mask 23.

FIG. 6E shows another example of an IMOD, where the movable reflective layer 14 is self supporting. In contrast with FIG. 6D, the implementation of FIG. 6E does not include the support posts 18. Instead, the movable reflective layer 14 contacts the underlying optical stack 16 at multiple locations, and the curvature of the movable reflective layer 14 provides sufficient support that the movable reflective layer 14 returns to the unactuated position of FIG. 6E when the voltage across the interferometric modulator is insufficient to cause actuation. The optical stack 16, which may contain a plurality of several different layers, is shown here for clarity including an optical absorber 16 a, and a dielectric 16 b. In some implementations, the optical absorber 16 a may serve both as a fixed electrode and as a partially reflective layer.

In implementations such as those shown in FIGS. 6A-6E, the IMODs function as direct-view devices, in which images are viewed from the front side of the transparent substrate 20, i.e., the side opposite to that upon which the modulator is arranged. In these implementations, the back portions of the device (that is, any portion of the display device behind the movable reflective layer 14, including, for example, the deformable layer 34 illustrated in FIG. 6C) can be configured and operated upon without impacting or negatively affecting the image quality of the display device, because the reflective layer 14 optically shields those portions of the device. For example, in some implementations a bus structure (not illustrated) can be included behind the movable reflective layer 14 which provides the ability to separate the optical properties of the modulator from the electromechanical properties of the modulator, such as voltage addressing and the movements that result from such addressing. Additionally, the implementations of FIGS. 6A-6E can simplify processing, such as (e.g., patterning).

FIG. 7 shows an example of a flow diagram illustrating a manufacturing process 80 for an interferometric modulator, and FIGS. 8A-8E show examples of cross-sectional schematic illustrations of corresponding stages of such a manufacturing process 80. In some implementations, the manufacturing process 80 can be implemented to manufacture, e.g., interferometric modulators of the general type illustrated in FIGS. 1 and 6, in addition to other blocks not shown in FIG. 7. With reference to FIGS. 1, 6 and 7, the process 80 begins at block 82 with the formation of the optical stack 16 over the substrate 20. FIG. 8A illustrates such an optical stack 16 formed over the substrate 20. The substrate 20 may be a transparent substrate such as glass or plastic, it may be flexible or relatively stiff and unbending, and may have been subjected to prior preparation processes, e.g., cleaning, to facilitate efficient formation of the optical stack 16. As discussed above, the optical stack 16 can be electrically conductive, partially transparent and partially reflective and may be fabricated, for example, by depositing one or more layers having the desired properties onto the transparent substrate 20. In FIG. 8A, the optical stack 16 includes a multilayer structure having sub-layers 16 a and 16 b, although more or fewer sub-layers may be included in some other implementations. In some implementations, one of the sub-layers 16 a, 16 b can be configured with both optically absorptive and conductive properties, such as the combined conductor/absorber sub-layer 16 a. Additionally, one or more of the sub-layers 16 a, 16 b can be patterned into parallel strips, and may form row electrodes in a display device. Such patterning can be performed by a masking and etching process or another suitable process known in the art. In some implementations, one of the sub-layers 16 a, 16 b can be an insulating or dielectric layer, such as sub-layer 16 b that is deposited over one or more metal layers (e.g., one or more reflective and/or conductive layers). In addition, the optical stack 16 can be patterned into individual and parallel strips that form the rows of the display.

The process 80 continues at block 84 with the formation of a sacrificial layer 25 over the optical stack 16. The sacrificial layer 25 is later removed (e.g., at block 90) to form the cavity 19 and thus the sacrificial layer 25 is not shown in the resulting interferometric modulators 12 illustrated in FIG. 1. FIG. 8B illustrates a partially fabricated device including a sacrificial layer 25 formed over the optical stack 16. The formation of the sacrificial layer 25 over the optical stack 16 may include deposition of a xenon difluoride (XeF₂)-etchable material such as molybdenum (Mo) or amorphous silicon (Si), in a thickness selected to provide, after subsequent removal, a gap or cavity 19 (see also FIGS. 1 and 8E) having a desired design size. Deposition of the sacrificial material may be carried out using deposition techniques such as physical vapor deposition (PVD, e.g., sputtering), plasma-enhanced chemical vapor deposition (PECVD), thermal chemical vapor deposition (thermal CVD), or spin-coating.

The process 80 continues at block 86 with the formation of a support structure e.g., a post 18 as illustrated in FIGS. 1, 6 and 8C. The formation of the post 18 may include patterning the sacrificial layer 25 to form a support structure aperture, then depositing a material (e.g., a polymer or an inorganic material, e.g., silicon oxide) into the aperture to form the post 18, using a deposition method such as PVD, PECVD, thermal CVD, or spin-coating. In some implementations, the support structure aperture formed in the sacrificial layer can extend through both the sacrificial layer 25 and the optical stack 16 to the underlying substrate 20, so that the lower end of the post 18 contacts the substrate 20 as illustrated in FIG. 6A. Alternatively, as depicted in FIG. 8C, the aperture formed in the sacrificial layer 25 can extend through the sacrificial layer 25, but not through the optical stack 16. For example, FIG. 8E illustrates the lower ends of the support posts 18 in contact with an upper surface of the optical stack 16. The post 18, or other support structures, may be formed by depositing a layer of support structure material over the sacrificial layer 25 and patterning portions of the support structure material located away from apertures in the sacrificial layer 25. The support structures may be located within the apertures, as illustrated in FIG. 8C, but also can, at least partially, extend over a portion of the sacrificial layer 25. As noted above, the patterning of the sacrificial layer 25 and/or the support posts 18 can be performed by a patterning and etching process, but also may be performed by alternative etching methods.

The process 80 continues at block 88 with the formation of a movable reflective layer or membrane such as the movable reflective layer 14 illustrated in FIGS. 1, 6 and 8D. The movable reflective layer 14 may be formed by employing one or more deposition steps, e.g., reflective layer (e.g., aluminum, aluminum alloy) deposition, along with one or more patterning, masking, and/or etching steps. The movable reflective layer 14 can be electrically conductive, and referred to as an electrically conductive layer. In some implementations, the movable reflective layer 14 may include a plurality of sub-layers 14 a, 14 b, 14 c as shown in FIG. 8D. In some implementations, one or more of the sub-layers, such as sub-layers 14 a, 14 c, may include highly reflective sub-layers selected for their optical properties, and another sub-layer 14 b may include a mechanical sub-layer selected for its mechanical properties. Since the sacrificial layer 25 is still present in the partially fabricated interferometric modulator formed at block 88, the movable reflective layer 14 is typically not movable at this stage. A partially fabricated IMOD that contains a sacrificial layer 25 may also be referred to herein as an “unreleased” IMOD. As described above in connection with FIG. 1, the movable reflective layer 14 can be patterned into individual and parallel strips that form the columns of the display.

The process 80 continues at block 90 with the formation of a cavity, e.g., cavity 19 as illustrated in FIGS. 1, 6 and 8E. The cavity 19 may be formed by exposing the sacrificial material 25 (deposited at block 84) to an etchant. For example, an etchable sacrificial material such as Mo or amorphous Si may be removed by dry chemical etching, e.g., by exposing the sacrificial layer 25 to a gaseous or vaporous etchant, such as vapors derived from solid XeF₂ for a period of time that is effective to remove the desired amount of material, typically selectively removed relative to the structures surrounding the cavity 19. Other etching methods, e.g. wet etching and/or plasma etching, also may be used. Since the sacrificial layer 25 is removed during block 90, the movable reflective layer 14 is typically movable after this stage. After removal of the sacrificial material 25, the resulting fully or partially fabricated IMOD may be referred to herein as a “released” IMOD.

In some implementations, the fabrication of the aforementioned electromechanical system devices (or IC devices) can employ a plasma-etch process, such as a reactive-ion etch or sputter-etch process, to etch material from a substrate. For example, a plasma-etch process may be employed to clean residual oxide or other materials from conductive contact surfaces prior to deposition of overlying conductors and/or to roughen surfaces of these devices at various stages of device fabrication. Such etching can be employed to improve electrical contact and/or adhesion of subsequent layers of material.

FIG. 9 shows an example of a cross-sectional schematic illustration of a stage in fabricating an interferometric modulator device 100. In particular, a contact area in the periphery of the device 100 is shown. In the illustrated implementation, a routing layer including a conductive material (e.g., a metal, such as aluminum) is patterned to form an interconnect 110 on a substrate 115. An insulating layer 120 (e.g., an oxide layer, such as SiO₂), is deposited onto the interconnect 110, and patterned to form vias 130 that open contact areas over the interconnect 110. One or more conductive layers 140 can be deposited over the interconnect 110 and the insulating layer 120 to fill the vias 130. In the illustrated implementation, a dielectric 150, such as SiON, can be patterned on one of the layers 140, and covered with a second of the layers 140. In the illustrated example, the layers 140 can include a metal, such as AlCu, sandwiching the dielectric 150, thus together defining a trilayer movable reflective layer similar to the movable reflective layer 14 of FIGS. 6D or 6E in the array region (not shown in FIG. 9) of the device 100. However, one having ordinary skill in the art will readily appreciate that such contact openings can be formed in various regions of integrated circuit or electromechanical devices.

In some implementations, a plasma-etch process can be employed prior to depositing the lower of the illustrated conductive layers 140 onto the insulating layer 120 and the interconnect 110, and can also be employed prior to depositing the upper of the conductive layers 140. A plasma-etch process can be employed to clean residual oxide (e.g., aluminum oxide) from the surface of the interconnect 110 that can form during the fabrication process. Plasma-etch processes can also be employed to roughen surfaces of the interferometric modulator 100. For example, a sputter-etch process can facilitate adhesion of one or more subsequent layers (e.g., the conductive layer 140) onto the interconnect 110 and/or the insulating layer 120. A person having ordinary skill in the art will understand that the configuration of the interferometric modulator 100 shown in FIG. 9 is for illustrative purposes only, and provides an example of a context of use for the implementation of the plasma-etch apparatus described further herein (e.g., FIGS. 10A-10B). A person having ordinary skill in the art will understand that the plasma-etch apparatus described herein can be employed, for example, during the fabrication of other portions of the interferometric modulator 100, or portions of other electromechanical systems and/or IC devices.

A plasma-etching tool (e.g., a reactive-ion etch (“RIE”) tool, sputter-etch tool, etc.) typically includes an etching chamber with an upper electrode that serves as an anode and a lower electrode that serves as a cathode positioned therein. A substrate to be etched is generally placed on and is supported by the cathode, which in operation is negatively biased with respect to the anode, typically using a radio-frequency (RF) power source. In an RIE process, the process can inherently provide a negative bias on the cathode with respect to the anode. In a sputter-etch process, a bias voltage can be directly controlled or applied to the cathode with respect to the anode and/or ground, to provide such negative bias to the cathode. The applied voltage can vary, depending on the size of the reactor, cathode, and/or anode, and/or the process conditions. The applied voltage can range from tens to thousands of volts. For example, the anode can be grounded and the cathode can be powered. Optionally, the chamber walls can also serve as part of the anode, e.g., by connecting conductive sidewalls to ground. A process gas is introduced into the etching chamber while the chamber is held to a low pressure, typically in the milliTorr range. The electric field established between the anode and the cathode causes plasma to form from the process gas, and positively charged ions of the plasma (e.g., argon ions, Ar⁺) are attracted to the cathode. Ion bombardment physically sputters or etches the substrate supported by the cathode.

In some plasma-etch chambers, the anode is configured as a showerhead plate for better gas flow distribution of inlet gases. The showerhead plate includes at least one hollow space or narrow gap with many small holes leading to the reaction space between the showerhead plate and the substrate. The combination of the interior narrow gap and relatively small holes creates back pressure and improves distribution of inlet gases over the substrate for more uniform etching across the substrate.

The surface areas of the components of these complex conventional showerhead configurations can absorb moisture and contaminants, particularly during routine maintenance procedures and during process after each substrate transfer because a substrate brings moisture and other contaminants into the chamber which can be absorbed to any surface inside the chamber such as inside the showerhead, chamber wall and liners, such that between processes or after maintenance very long pump-down processes are employed to achieve defined moisture/contaminant levels before processing the next substrate. The holes in the showerhead plates restrict the flow of gas from the internal space of the showerhead into the etch chamber, which also increases the pump-down time. Additionally, conventional showerheads can often have chemically inert anodized aluminum surfaces; however, anodized aluminum is also porous and absorbs moisture, thus, further increasing the pump-down cycle time.

Disclosed herein are implementations of a plasma-etch system that can include a substantially solid or non-hollow anode, such as a simple liner plate, that can be employed instead of a showerhead. Replacing the showerhead with a non-hollow anode at the inlet can reduce the overall surface area of the anode, hence, reducing the pump-down cycle time and increasing tool throughput. In some implementations, the anode can include a bare (e.g., unanodized) metal (e.g., aluminum, stainless steel, or molybdenum), which can help further reduce moisture absorption and pump-down time. The chamber is configured for plasma etch, and is particularly useful for reducing pump-down time for inert sputter-etching (e.g., Argon sputter-etch). Sputter-etching is typically not as sensitive to non-uniformities. For applications in which greater uniformity is desired for gas distribution, the anode can include a perforated plate to facilitate the free flow of gas through and around the edges of the plate. Nonetheless, such a perforated plate generally has a smaller overall surface area than the showerhead in many conventional designs.

In some implementations, the anode can be configured to be retrofit and/or easily replaceable, so that it can be used in conjunction with existing plasma-etch equipment, and/or can be interchangeable with a showerhead, to allow a tool to be used for any of a variety of plasma processes.

FIG. 10A shows an example of a cross-sectional side view of a plasma-etch system 200. FIG. 10B shows an example of a cross-sectional top view of a plasma-etch system taken along lines 10B-10B of FIG. 10A. Referring to FIGS. 10A-10B, the plasma-etch system 200 can include a plasma-etch reactor 205. The plasma-etch reactor 205 can include a plasma-etch reaction chamber 210, a process gas inlet, or inlet structure 220, and a power source to produce a plasma. In addition to creating an alternating field conducive to plasma generation within the chamber 210 (e.g., by application of RF power to internal or external electrodes), the reactor 205 includes electrodes to produce a bias. For example, the illustrated reactor 205 includes a cathode 230 that can be negatively biased with respect to an anode 240.

The reaction chamber 210 can be any shape suitable to support and conduct a plasma-etch process on a substrate 300 positioned and supported within an interior volume of the reaction chamber 210. The substrate 300 can include any of a number of different substrates used to form electromechanical system devices and/or integrated circuit devices, such as glass, silicon, and the like. In an implementation, the substrate 300 can include a rectangular glass substrate ranging from a size of G1 (300×350 mm) to G10 (2850×3050 mm). The length of the substrate 300 can range from about 350 mm to about 3050 mm, or more particularly, from about 470 mm to about 1850 mm, or more particularly, from about 650 mm to about 1250 mm. The width of the substrate 300 can range from about 300 mm to about 2850 mm, or more particularly, from about 370 mm to about 1500 mm, or more particularly, from about 550 mm to about 1100 mm. In one example, the substrate 300 can be a rectangular glass substrate with a length x width of about 920 mm×730 mm.

The plasma-etch reaction chamber 210 can be configured to form an interior volume within sidewalls 211, a top 212 and a base (e.g., cathode 230). In one implementation, the interior volume of the reaction chamber 210 can range from approximately 100 liters to 300 liters for G4.5 Size Glass. For G10 size, it can be 1500 liters or more. The chamber 210 can include any of many materials suitable for a plasma-etch process, such as a metal and/or metal alloy (e.g., aluminum, stainless steel, etc.). The chamber 210 can be suitably configured to be sealed and held to a particular pressure (e.g., a low pressure in the millitorr range) during at least portions of the plasma-etch process.

The process gas inlet structure 220 can have any suitable configuration to facilitate fluid communication between the inlet structure 220 and the interior of the reaction chamber 210, such as, for example, to facilitate the introduction of process gases into the reaction chamber 210. In the illustrated example, the inlet structure 220 can include an inlet body 222 with a channel 221 extending therethrough. The inlet body 222 and the channel 221 can be configured to extend through a portion (e.g., the top 212) of the reaction chamber 210. The inlet body 222 can be attached to a portion of the reaction chamber 210 in any suitable manner, such as with a flange 223 extending from the inlet body 222.

The cathode 230 can include a substrate support, illustrated here as a pedestal body 231, suitably configured to provide support to the substrate 300 and to position the substrate 300 within the reaction chamber 210. In some implementations, the cathode 230 can be configured to be movable (e.g., in the directions shown by arrows 510) between a loading position and a processing position, to facilitate the loading and unloading of the substrate 300 to and from the reaction chamber 210. The cathode 230 is shown in FIGS. 10A and 10B in a processing position. The cathode 230 can be movable using any suitable drive mechanism 233. A person having ordinary skill in the art will understand that the system 200 (e.g., reactor 205) can be configured in other ways to facilitate loading and unloading a substrate into and out of the reaction chamber 210. For example, the cathode can be stationary, and/or the anode and/or the top can be configured to move, to allow the substrate to be loaded and unloaded from an upper portion of the reaction chamber. In other examples, one or more of the sidewalls of the chamber can include an opening or gate valve through which the substrate can be loaded and unloaded.

The anode 240 can be positioned within the reaction chamber 210 between the inlet structure 220 and the cathode 230. In some implementations, the anode 240 can be supported by and/or attached to one or more walls of the reaction chamber 210 (e.g., the top 212). In the implementation illustrated, the anode 240 is attached to a lower portion of the inlet structure 220 that extends into the interior volume of the chamber 210. A person having ordinary skill in the art will understand that any of a number of suitable configurations that support and attach the anode 240 within the chamber 210 can be employed. In the illustrative implementation, the anode 240 is attached to a flange 224 that extends outwardly from the inlet body 222 of the inlet structure 220.

The anode 240 can include a liner plate 241 positioned within the reaction chamber 210 between the inlet structure 220 and the cathode 230. The liner plate 241 can be configured with any suitable shape, size and material that allows application of a voltage differential between the anode 240 and the cathode 230 during a plasma-etch process, and that allows the flow of a process gas around the plate 241, as described further herein. In some implementations, the liner plate 241 is sized, shaped, and positioned within the reaction chamber 210 such that a gap 216 is formed between the liner plate 241 (e.g., edges 244 of the liner plate 241) and the walls of the reaction chamber 210 (e.g., the sidewalls 211).

The anode 240, the inlet structure 220, and/or the reaction chamber 210 can be configured and positioned with respect to each other such that when a process gas is introduced into the reaction chamber from the inlet structure 220, at least a portion of the process gas is allowed to flow across an upper surface of the anode 240 (e.g., the upper surface 243 of the liner plate 241). In some implementations, at least a portion of the process gas is allowed to flow from the inlet structure 220 in a direction that strikes, or impinges upon an upper surface of the anode 240 (e.g., through the channel 221 in direction 501). In some implementations, the anode 240, the inlet structure 220, and/or the reaction chamber 210 can be configured and positioned with respect to each other such that the process gas can flow around the edges 244 of the plate 241. Such flow of the process gas can be facilitated in any of a variety of ways.

The inlet structure 220 can be integrally or separately formed with respect to the liner plate 241, and can be attached thereto in any of a number of different ways (e.g., snap fit, press fit, threads, fasteners and the like). In the illustrated implementation, the inlet structure 220 can include one or more fasteners (e.g., screws or bolts) 227 to attach the liner plate 241 to a portion of the inlet structure 220 (e.g., the inlet body 222). It will be understood that the number and mounting pattern of fasteners 227 shown in FIG. 10B is for illustrative purposes only, and that any of a number of quantities and mounting patterns can be implemented. The inlet structure 220 can include one or more spacers 225 that can space the liner plate 241 apart from a lower portion of the inlet body 222 (e.g., one or more lower outlets or openings 226 of the channel 221), forming a vertical gap 246 within the inlet structure 220 between the liner plate 241 and the inlet body 222. As illustrated in FIG. 10A, the vertical gap 246 between the liner plate 241 and the inlet body 222 allows at least a portion of the process gas to flow from the lower outlet or opening 226 (e.g., in the direction shown by arrow 501), and to strike an upper surface 243 of the liner plate 241, thus redirecting at least a portion of the process gases to flow parallel to and above the upper surface 243 of the liner plate 241 (e.g., in the direction shown by arrows 502).

Referring to FIG. 10B, the spacers 225 and/or the fasteners 227 can be spaced apart relative to each other, to form one or more horizontal gaps or openings 247 therebetween. Such horizontal gaps or openings 247 can allow at least a portion of the process gas to flow from the inlet body 222 of inlet structure 220 (e.g., the outlet 226), around or between the spacers 225 and/or the fasteners 227, from the inlet structure 220, and across the upper surface 243 of the liner plate 241, in the direction shown by directional arrows 502. In some implementations, at least a portion of the process gas can flow across the upper surface 243 of the liner plate 241, and around the edges 244 of the plate 241 (e.g., through gaps 216, as shown by directional arrows 503). In some implementations, an unobstructed flowpath of at least a portion of the gas can be formed across the upper surface 243 from the outlet 226, to and around the edges 244 of the plate 241. At least a portion of the process gas can then flow from around the edges 244 to a plasma reaction zone 260 as shown in FIG. 10A, which is generally positioned between the anode 240 (e.g., a lower surface 245 of the liner plate 241) and the cathode 230. In some implementations, the liner plate 241 can be solid and/or can be substantially unperforated through its thickness, such that the process gas cannot flow through the liner plate 241.

FIG. 10C shows an example of a cross-sectional side view of a plasma-etch system. FIG. 10D shows an example of a cross-sectional top view of a plasma-etch system taken along lines 10D-10D of FIG. 10C. Referring to FIGS. 10C and 10D, the anode 240, the inlet structure 220, and/or the reaction chamber 210 can be configured and positioned with respect to each other such that the process gas can flow through the plate 241. As shown, the liner plate 241 can include one or more apertures or holes 242 extending through its thickness, to allow at least a portion of the process gas to flow through the liner plate 241, to the plasma reaction zone 260, as shown by directional arrows 504. The holes 242 can be any of a number of quantities, sizes, shapes, and/or positions on liner plate 241 to allow one or more different flowpaths through liner plate 241. In one implementation, the holes 242 are configured to allow at least a portion of the process gas to flow across the upper surface 243 of liner 241 in the directions shown by directional arrows 502, as described with respect to FIGS. 10A and 10B, such that despite some gas passing through the holes 242, some process gas can flow across the upper surface 243 of the liner plate 241, and around the edges 244 of the plate 241 (e.g., through gaps 216, as shown by directional arrows 503), to the plasma reaction zone 260.

A person having ordinary skill in the art will understand that the implementations of the plasma-etch system 200 shown in FIGS. 10A through 10D are for illustrative purposes only. A person having ordinary skill in the art will understand that system 200 and its components or sub-components, such as the liner 241, the inlet structure 220, and/or the reaction chamber 210 can be configured in many different ways and combinations that facilitate various combinations of the aforementioned process gas flowpaths while eliminating the aforementioned showerheads and complex flow distribution structure and flowpaths employed in conventional plasma-etch tools. For example, although the channel 221 is shown oriented approximately perpendicular to the upper surface 243 of the liner plate 241, the outlet or opening 226 can be positioned at other angles relative to the upper surface 243 of the liner plate 241 that allow the process gas to flow from the lower outlet 226 and strike an upper surface of the liner plate 241. In some implementations, the body 222 of inlet structure 220 can be mounted directly to the liner plate 241 (e.g., without the spacers 225), and the inlet structure 220 can include one or more outlet openings above the upper surface 243, configured to direct process gas outwardly (e.g., radially outwardly) from the inlet structure 220 across the upper surface 243 of the liner plate 241 in the direction shown by arrows 502. In some implementations, the inlet structure 220 can include one or more outlet openings extending through a sidewall of the body 222, and configured to direct process gas across the upper surface 243 of the anode 240. Gas exiting such outlet openings need not impinge perpendicularly upon the upper surface before exiting such side holes. Replacing a showerhead on a plasma-etch tool with the liner plate 241 can facilitate various combinations of the aforementioned process gas flows and can reduce the pump-down cycle time of a sputter-etch process, and thus increase tool throughput.

The liner plate 241 can include any of a number of different materials. Conventional showerhead designs are coated (e.g. anodized) with a protective coating or insulator, such as aluminum oxide. Such coating is used to protect the showerhead from corrosion when the showerhead is used in a reactive-ion etch process. However, in a sputter-etch process that uses inert gases such as argon, corrosion from reactants is less of an issue, and an anodized coating can absorb water and increase outgassing relative to a similar unanodized component. Such water absorption and increased outgassing increases the pump-down time of a sputter-etch reaction chamber between processes or after maintenance. In some implementations, the liner plate 241 can include a bare (e.g., unanodized or uncoated) metal or metal alloy, such as stainless steel, Mo, aluminum, etc. to reduce moisture absorption and pump-down time in a sputter-etch process.

In some implementations, one or more surfaces of the liner plate 241 (e.g., the lower surface 245 facing the substrate 300 when the liner plate 241 is positioned within the chamber 210) can be roughened, through a sandblasting, bead blasting, arc spray, plasma spray, or other roughening process. The liner plate 241 can be configured to be sufficiently rough to allow a layer of material to adhere to the surface of the liner plate 241 during a sputter-etch process (e.g., to prevent flaking), while controlling the surface area of the liner plate 241 to a level that reduces outgassing. In one implementation, the surface area of the liner plate 241 (e.g., the lower surface 245 facing the substrate 300) is configured at an average roughness R_(a) ranging from approximately 63 μm rms to 250 μm rms. Film flaking on the smooth surface can happen when the film thickness reaches several thousands angstrom. Film flaking on the roughened surface typically happens when the thickness reaches more than several microns but it depends on material and stress of the film. The rough surface can have better film adhesion and help reducing particles. However, the rough surface tends to have more moisture absorption and cause slower pumping speed. It also depends on the roughness. The roughness in one implementation disclosed herein (Ra: 63-250) can effectively reduce flaking but the pumping speed of the single plate liner with this roughness is much faster than the conventional showerhead structure.

The plasma-etch system 200 (e.g., reactor 205) can include one or more structures to provide additional or alternative support to the liner plate 241. In the implementation illustrated, the plasma-etch system 200 includes one or more straps 242 extending between a portion (e.g., the upper surface 243) of the anode 240 and the reaction chamber 210 (e.g., a lower surface of the top 212).

The top 212, sidewalls 213, the inlet structure 220, straps 242, and/or the liner plate 241 can be electrically connected or isolated with respect to each other, in any of a number of ways, to facilitate desired electrical biasing for controlling directionality of the sputter etch. Any or all of a portion or all of these components can include an electrically conductive or insulating material to provide such electrical connectivity or isolation. In some implementations, an insulating structure can be positioned between any or all of these components to provide such isolation. Such isolation can allow a potential difference (e.g., voltage) between one or more of these components. For example, the liner plate 241, the inlet structure 220, the top 212, and sidewalls 211 can include an electrically conductive material, and straps 242, as shown in FIGS. 10A and 10C, can be provided to allow these components to be biased to the same potential as the anode 240 (e.g., ground). In other arrangements, the liner plate and the inlet can be electrically isolated from the top and sidewalls.

Test results using a conventional plasma-etch chamber with an internal volume of 285 liters, and with a conventional showerhead replaced with an implementation of the aforementioned liner plate, have reduced the pumping time to reach a base pressure of 1.00×10⁻⁵ Pa within the plasma-etch chamber from 35 hours with a showerhead to 22 hours with the non-hollow liner plate 241 of FIG. 10A. Example test results using a conventional plasma-etch chamber with an internal volume of 285 liters, and with a conventional showerhead replaced with one implementation of the aforementioned liner plate, have reduced the pumping time to reach a residual gas analyzer (RGA) detected moisture level corresponding to a partial pressure of water (H₂O) of 8e-8 torr within the plasma-etch chamber from 28 hours with a showerhead to 20 hours with the non-hollow liner plate 241 of FIG. 10A. In an implementation of the aforementioned liner plate, a maintenance procedure to clean the plasma-etch chamber of moisture and contamination that was previously conducted every week can now be conducted less frequently, such as, for example, every two weeks, or once a month, etc. Thus, using the aforementioned liner plate, more than 5000 substrates can be processed for a total of more than 5000 sputtering cycles prior to cleaning the plasma-etch chamber in some implementations, whereas using the same plasma-etch chamber with a conventional showerhead design only 1500-2500 substrates can be processed for a total of 1500-2500 sputtering cycles.

Plasma-etch systems can additionally include one or more wall liners covering one or more inner surfaces of the reaction chamber. Such wall liners can be configured with certain materials and properties (e.g., roughness) to facilitate cleaning of the reaction chamber and to control the level of adhesion thereto of the materials and the films formed during the plasma-etch process. Continuing to refer to FIGS. 10A and 10B, the plasma-etch system 200 can include one or more wall liners 213 configured to cover a portion of the sidewalls 211. In some implementations, the wall liner 213 can be configured to reduce conductive films formed during a sputter-etch process, which may shield the cathode 230 and reduce the efficiency of, or reduce the likelihood of plasma ignition, as described further herein.

The cathode 230 can include a flange 232 (e.g., an annular flange) extending outwardly from the body 231 to help seal the reaction chamber 210 when the substrate 300 is loaded into process position. One or more insulating portions or layers can be configured to cover one or more portions of the cathode 230, to isolate the cathode 230 from the ground (e.g., the walls of the chamber 210) and to facilitate the formation of the bias between the anode 240 and the cathode 230 described further herein. The insulating portions can include any of a number of different suitable insulating materials, such as ceramic. In the implementation illustrated, a first insulator 234 can be configured to cover an upper surface and a portion of a side surface of the body 231. A second insulator 235 can be configured to cover the remainder of the side surface of the body 231, and an upper surface of the flange 232. The second insulator 235 (in conjunction with, in some implementations, additional structures and mechanisms) can be configured to engage with a lower portion 217 of the sidewall 211 when the cathode 230 is in a loading position (e.g., to seal the chamber 210). The insulators 234 and 235, which can be integral with one another, can insulate the cathode 230 from the remainder of the chamber 210 (e.g., from the sidewall 211) and/or from the substrate 300.

The insulators 234 and 235 can be configured such that a horizontal gap 250 is formed between the sidewall 211, specifically the lower portion 217 of the sidewall 211, and the insulator 234. During the sputter-etch of conductive films, such as Mo, the sputtered material can deposit on any exposed surface in the chamber 210. Thus, a conductive film may form on the insulators 234 and 235, the sidewalls 211 (including the exposed portions of the lower portion 217), and any liners positioned on the sidewalls 211. In some configurations, this conductive film can form a layer that extends across the substrate 300, across the exposed surfaces of the insulators 234 and 235, into the horizontal gap 250, across the exposed surfaces of the sidewalls 211, and across the liners positioned on the sidewalls 211. Once such a conductive layer is formed, there is a risk that the RF power used to form the plasma within the plasma-etch process can flow along the surface of the conductive layer and to the ground (e.g., the chamber wall). Such a conductive film can cause RF power loss to the cathode 230, which can reduce the likelihood of plasma ignition and reduce the efficiency of the plasma-etch process.

In the illustrated implementation, the liner 213 includes a first member 214 configured to be mounted on a wall of the chamber 210. The illustrated liner 213 also includes a second member 215 that can extend outwardly from a lower portion of the first member 214 (e.g., from an end of the first member 214). The second member 215 can be configured such that when the liner 213 is positioned on the sidewall 211, the second member 215 extends over (e.g., above) the horizontal gap 250, with a vertical gap 251 formed between the lower surface of the second member 215 and the upper surface of the insulator 234. Such positioning and configuration of the liner 213 can reduce sputtered material from the etched substrate 300 being deposited under the second member 215 and forming a conductive film within the horizontal gap 250 and on portions of the insulator 234, the second insulator 235 and the sidewall 211 (including the exposed surfaces of the lower portion 217) that are positioned under the second member 215. In some implementations, the second member 215 can extend beyond the edge of the horizontal gap 250 (e.g., over a portion of the liner 234) by a distance ranging from approximately a few mm to a few cm. The second member 215 can be long enough to cover the gap 250. The length of the second member 215 can be a few mm wider than the gap 250. The width of the overlap of the horizontal gap 250 can be determined based on balancing performance and the space available. In some implementations, it can be about 5 mm to 15 mm. The liner 213 can be positioned and configured such that the vertical gap 251 is narrow enough to substantially inhibit sputtered material from depositing within the horizontal gap 250, while being wide enough such that the conductive film from the sputtering process does not extend across the vertical gap 251 (e.g., from the second member 215 to the substrate 300 and/or the first insulator 234) in the course of a production run. In some implementations, the liner 213 can be positioned and configured such that the length of the vertical gap 251 ranges from approximately 0.3-1 mm.

A person having ordinary skill in the art will understand that the liner 213 is not limited to the L-shape shown in FIGS. 10A and 10B, and can be configured in any of a variety of shapes that can serve to extend over and shield the gap 250. For example, the liner 213 can be configured such that the second member 215 can extend from various positions along the length of the first member 214, and/or at various angles with respect to the first member 214. In some implementations, the second member 215 can be a curved member that curves inwardly within the chamber 210, while still extending over the horizontal gap 250 and forming the vertical gap 251.

A person having ordinary skill in the art will also understand that the implementations of the liner 213 and the liner plate 241 described herein are shown as being used in combination with each other in FIGS. 10A and 10B for illustrative purposes only. However, either or both the liner 213 and/or the liner plate 241 can be implemented in a plasma-etch tool.

FIG. 10E shows an example of a system block diagram illustrating plasma-etch system 200 that includes a control system or controller 270 to control various features of, or methods provided by, one or more other components of plasma-etch system 200, such as reactor 205. The plasma-etch system 200 can be controlled electronically, but can include other types of control sub-systems or components such as pneumatic or hydraulic. The control system 270 can include any of a number of configurations, and can include any of a variety of controllers, user interfaces, buttons, switches, circuits, and the like. The control system 270 can control any of the number of components of the reactor 205. For example, the control system 270 can control the flow of process gas into the reaction chamber; the power to the electrodes within the reaction chamber; and the movement of the substrate to and from the reaction chamber. In some implementations, the control system 270 can be in communication with, and/or can be a part of, a control system and/or network within a facility for fabricating electromechanical system devices and/or integrated circuit devices.

In some implementations, the control system 270 can be hard-wired to the components or sub-components of plasma-etch system 200, or can be configured to control the components or sub-components wirelessly. The control system 270 can optionally be in communication with a network 280. The control system 270 can be attached to a portion of plasma-etch system 200 (e.g., reactor 205) or can be separate from such a portion of plasma-etch system 200. In some implementations, the control system 270 can be configured to control various aspects of the plasma-etch system 200 remotely (e.g., through a telecommunication system, wirelessly, and/or an additional control system that sends a control signal to control system 270, etc.), that allow a user to remotely interact with and control one or more plasma-etch systems 200 and their components, e.g., from a central station. The control system 270 can include a processor 272, a central processing unit (CPU), a microcontroller, or a logic unit. In some implementations, the control system 270 can include a memory 274, which can be local to the remainder of control system 270, or can be located remote from the remainder of control system 270 (e.g., through cloud computing methods).

FIG. 10F shows an example of a flow diagram illustrating a method of plasma-etching a substrate. As illustrated in FIG. 10F, the method 400 can include providing a plasma-etch reaction chamber, an inlet configured to be in fluid communication with the reaction chamber, a cathode configured to support a substrate, and an anode within the reaction chamber between the inlet and the cathode at block 410. The cathode can be configured to be negatively biased with respect to the anode. At block 420, the method includes introducing a process gas into the reaction chamber such that at least a portion of the process gas strikes an upper surface of the anode and flows across the upper surface and around the edges of the anode. At block 430, the method includes igniting a plasma between the anode and the cathode. In some implementations, the method can further include etching material from at least a portion of a substrate supported by the cathode. In some implementations, the etching can include sputter-etching. In some implementations, the process gas is introduced into the reaction chamber by flowing a portion of the process gas through one or more holes extending through a thickness of the liner plate. In some implementations, the process gas includes argon.

FIGS. 11A and 11B show examples of system block diagrams illustrating a display device 40 including a plurality of interferometric modulators. The display device 40 can be, for example, a cellular or mobile telephone. However, the same components of the display device 40 or slight variations thereof are also illustrative of various types of display devices such as televisions, e-readers and portable media players.

The display device 40 includes a housing 41, a display 30, an antenna 43, a speaker 45, an input device 48, and a microphone 46. The housing 41 can be formed from any of a variety of manufacturing processes, including injection molding, and vacuum forming. In addition, the housing 41 may be made from any of a variety of materials, including, but not limited to: plastic, metal, glass, rubber, and ceramic, or a combination thereof. The housing 41 can include removable portions (not shown) that may be interchanged with other removable portions of different color, or containing different logos, pictures, or symbols.

The display 30 may be any of a variety of displays, including a bi-stable or analog display, which can be manufactured using various implementations of the etching equipment as described herein. The display 30 also can be configured to include a flat-panel display, such as plasma, EL, OLED, STN LCD, or TFT LCD, or a non-flat-panel display, such as a CRT or other tube device. In addition, the display 30 can include an interferometric modulator display, as described herein.

The components of the example display device 40 are schematically illustrated in FIG. 11B. The display device 40 includes a housing 41 and can include additional components at least partially enclosed therein. For example, the display device 40 includes a network interface 27 that includes an antenna 43 which is coupled to a transceiver 47. The transceiver 47 is connected to a processor 21, which is connected to the conditioning hardware 52. The conditioning hardware 52 may be configured to condition a signal (e.g., filter a signal). The conditioning hardware 52 is connected to a speaker 45 and a microphone 46. The processor 21 is also connected to an input device 48 and a driver controller 29. The driver controller 29 is coupled to a frame buffer 28, and to an array driver 22, which in turn is coupled to a display array 30. A power supply 50 can provide power to all components as defined by the particular display device 40 design.

The network interface 27 includes the antenna 43 and the transceiver 47 so that the display device 40 can communicate with one or more devices over a network. The network interface 27 also may have some processing capabilities to relieve, e.g., data processing requirements of the processor 21. The antenna 43 can transmit and receive signals. In some implementations, the antenna 43 transmits and receives RF signals according to the IEEE 16.11 standard, including IEEE 16.11(a), (b), or (g), or the IEEE 802.11 standard, including IEEE 802.11a, b, g or n. In some other implementations, the antenna 43 transmits and receives RF signals according to the BLUETOOTH standard. In the case of a cellular telephone, the antenna 43 is designed to receive code division multiple access (CDMA), frequency division multiple access (FDMA), time division multiple access (TDMA), Global System for Mobile communications (GSM), GSM/General Packet Radio Service (GPRS), Enhanced Data GSM Environment (EDGE), Terrestrial Trunked Radio (TETRA), Wideband-CDMA (W-CDMA), Evolution Data Optimized (EV-DO), NEV-DO, EV-DO Rev A, EV-DO Rev B, High Speed Packet Access (HSPA), High Speed Downlink Packet Access (HSDPA), High Speed Uplink Packet Access (HSUPA), Evolved High Speed Packet Access (HSPA+), Long Term Evolution (LTE), AMPS, or other known signals that are used to communicate within a wireless network, such as a system utilizing 3G or 4G technology. The transceiver 47 can pre-process the signals received from the antenna 43 so that they may be received by and further manipulated by the processor 21. The transceiver 47 also can process signals received from the processor 21 so that they may be transmitted from the display device 40 via the antenna 43.

In some implementations, the transceiver 47 can be replaced by a receiver. In addition, the network interface 27 can be replaced by an image source, which can store or generate image data to be sent to the processor 21. The processor 21 can control the overall operation of the display device 40. The processor 21 receives data, such as compressed image data from the network interface 27 or an image source, and processes the data into raw image data or into a format that is readily processed into raw image data. The processor 21 can send the processed data to the driver controller 29 or to the frame buffer 28 for storage. Raw data typically refers to the information that identifies the image characteristics at each location within an image. For example, such image characteristics can include color, saturation, and gray-scale level.

The processor 21 can include a microcontroller, CPU, or logic unit to control operation of the display device 40. The conditioning hardware 52 may include amplifiers and filters for transmitting signals to the speaker 45, and for receiving signals from the microphone 46. The conditioning hardware 52 may be discrete components within the display device 40, or may be incorporated within the processor 21 or other components.

The driver controller 29 can take the raw image data generated by the processor 21 either directly from the processor 21 or from the frame buffer 28 and can re-format the raw image data appropriately for high speed transmission to the array driver 22. In some implementations, the driver controller 29 can re-format the raw image data into a data flow having a raster-like format, such that it has a time order suitable for scanning across the display array 30. Then the driver controller 29 sends the formatted information to the array driver 22. Although a driver controller 29, such as an LCD controller, is often associated with the system processor 21 as a stand-alone Integrated Circuit (IC), such controllers may be implemented in many ways. For example, controllers may be embedded in the processor 21 as hardware, embedded in the processor 21 as software, or fully integrated in hardware with the array driver 22.

The array driver 22 can receive the formatted information from the driver controller 29 and can re-format the video data into a parallel set of waveforms that are applied many times per second to the hundreds, and sometimes thousands (or more), of leads coming from the display's x-y matrix of pixels.

In some implementations, the driver controller 29, the array driver 22, and the display array 30 are appropriate for any of the types of displays described herein. For example, the driver controller 29 can be a conventional display controller or a bi-stable display controller (e.g., an IMOD controller). Additionally, the array driver 22 can be a conventional driver or a bi-stable display driver (e.g., an IMOD display driver). Moreover, the display array 30 can be a conventional display array or a bi-stable display array (e.g., a display including an array of IMODs). In some implementations, the driver controller 29 can be integrated with the array driver 22. Such an implementation is common in highly integrated systems such as cellular phones, watches and other small-area displays.

In some implementations, the input device 48 can be configured to allow, e.g., a user to control the operation of the display device 40. The input device 48 can include a keypad, such as a QWERTY keyboard or a telephone keypad, a button, a switch, a rocker, a touch-sensitive screen, or a pressure- or heat-sensitive membrane. The microphone 46 can be configured as an input device for the display device 40. In some implementations, voice commands through the microphone 46 can be used for controlling operations of the display device 40.

The power supply 50 can include a variety of energy storage devices. For example, the power supply 50 can be a rechargeable battery, such as a nickel-cadmium battery or a lithium-ion battery. The power supply 50 also can be a renewable energy source, a capacitor, or a solar cell, including a plastic solar cell or solar-cell paint. The power supply 50 also can be configured to receive power from a wall outlet.

In some implementations, control programmability resides in the driver controller 29 which can be located in several places in the electronic display system. In some other implementations, control programmability resides in the array driver 22. The above-described optimization may be implemented in any number of hardware and/or software components and in various configurations.

The various illustrative logics, logical blocks, modules, circuits and algorithm steps described in connection with the implementations disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. The interchangeability of hardware and software has been described generally, in terms of functionality, and illustrated in the various illustrative components, blocks, modules, circuits and steps described above. Whether such functionality is implemented in hardware or software depends upon the particular application and design constraints imposed on the overall system.

The hardware and data processing apparatus used to implement the various illustrative logics, logical blocks, modules and circuits described in connection with the aspects disclosed herein may be implemented or performed with a general purpose single- or multi-chip processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, or, any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. In some implementations, particular steps and methods may be performed by circuitry that is specific to a given function.

In one or more example aspects, the functions described may be implemented in hardware, digital electronic circuitry, computer software, firmware, including the structures disclosed in this specification and their structural equivalents thereof, or in any combination thereof. Implementations of the subject matter described in this specification also can be implemented as one or more computer programs, i.e., one or more modules of computer program instructions, encoded on a computer storage media for execution by, or to control the operation of, data processing apparatus.

Various modifications to the implementations described in this disclosure may be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other implementations without departing from the spirit or scope of this disclosure. Thus, the disclosure is not intended to be limited to the implementations shown herein, but is to be accorded the widest scope consistent with the claims, the principles and the novel features disclosed herein. Additionally, a person having ordinary skill in the art will readily appreciate, the terms “upper” and “lower” are sometimes used for ease of describing the figures, and indicate relative positions corresponding to the orientation of the figure on a properly oriented page, and may not reflect the proper orientation of the IMOD as implemented.

Certain features that are described in this specification in the context of separate implementations also can be implemented in combination in a single implementation. Conversely, various features that are described in the context of a single implementation also can be implemented in multiple implementations separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.

Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. In certain circumstances, multitasking and parallel processing may be advantageous. Moreover, the separation of various system components in the implementations described above should not be understood as requiring such separation in all implementations, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products. Additionally, other implementations are within the scope of the following claims. In some cases, the actions recited in the claims can be performed in a different order and still achieve desirable results. 

1. A plasma-etch system, comprising: a plasma-etch reaction chamber; an inlet configured to be in fluid communication with the reaction chamber; a cathode including a substrate support positioned within the reaction chamber; and a non-hollow anode positioned within the reaction chamber between the inlet and the cathode, wherein the inlet is configured to introduce a process gas into the reaction chamber such that at least a portion of the process gas is allowed to flow across an upper surface of the anode and around edges of the anode.
 2. The plasma-etch system of claim 1, wherein the plasma-etch reaction chamber includes a sputter-etch reaction chamber.
 3. The plasma-etch system of claim 1, wherein the anode includes a liner plate.
 4. The plasma-etch system of claim 1, wherein the anode includes an exposed metal without an anodized coating.
 5. The plasma-etch system of claim 1, wherein the anode is substantially unperforated through its thickness.
 6. The plasma-etch system of claim 1, wherein the anode includes one or more holes extending through its thickness.
 7. The plasma-etch system of claim 1, wherein the inlet defines one or more openings positioned above the upper surface of the anode and is configured to allow the at least a portion of the process gas to flow from the inlet and across the upper surface of the anode.
 8. The plasma-etch system of claim 7, wherein the one or more openings are spaced apart from the upper surface of the anode to define a vertical gap between the upper surface of the anode and the inlet.
 9. The plasma-etch system of claim 8, wherein the one or more openings are aligned with respect to the upper surface of the anode such that the at least a portion of the process gas strikes the upper surface.
 10. The plasma-etch system of claim 8, further including a plurality of spacers between the inlet and the upper surface of the anode, wherein a horizontal gap extends between each two adjacent spacers in the plurality of spacers, to allow the at least a portion of the process gas to flow from the inlet, through the vertical and horizontal gap, and across the upper surface of the anode.
 11. The plasma-etch system of claim 1, further including a control system.
 12. The plasma-etch system of claim 11, wherein the control system further includes a processor.
 13. The plasma-etch system of claim 11, wherein the control system is communicatively coupled to a network.
 14. A plasma-etch system, comprising: a chamber for a plasma-etch reaction; a cathode means for conducting electric charges; an anode means for conducting electric charges; and fluid communication means for providing fluid into the chamber and guiding at least some of the fluid across an upper surface of the anode means, around outer edges of the anode means and into a plasma reaction zone between the anode means and the cathode means.
 15. The plasma-etch system of claim 14, wherein the chamber includes a sputter-etch reaction chamber.
 16. The plasma-etch system of claim 14, wherein the fluid communication means includes a gas inlet and the anode means includes a non-hollow plate positioned between the gas inlet and the cathode means.
 17. The plasma-etch system of claim 14, wherein the anode means includes an exposed metal without an anodized coating.
 18. The plasma-etch system of claim 14, wherein the anode means includes a substantially unperforated plate.
 19. The plasma-etch system of claim 14, wherein the anode means includes a plate defining a plurality of holes extending through a thickness of the plate such that gas can flow therethrough.
 20. A method of plasma-etching a substrate, comprising: providing a plasma-etch reaction chamber, an inlet configured to be in fluid communication with the reaction chamber, a cathode configured to support a substrate, and an anode within the reaction chamber between the inlet and the cathode, wherein the cathode is configured to be negatively biased with respect to the anode; introducing a process gas into the reaction chamber such that at least a portion of the process gas strikes an upper surface of the anode and flows across the upper surface and around the edges of the anode; and igniting a plasma between the anode and the cathode.
 21. The method of claim 20, further including etching material from at least a portion of a substrate supported by the cathode.
 22. The method of claim 21, wherein etching includes sputter-etching.
 23. The method of claim 20, wherein introducing further includes flowing a portion of the process gas through one or more holes extending through a thickness of the liner plate.
 24. The method of claim 20, wherein introducing includes introducing argon into the reaction chamber. 